The general principle of transmitting data by dividing it into several interleaved bit streams, and using these bit streams to modulate several carriers is well known. Modems using this principle employ what is referred to as Discrete Multitone (DMT) modulation and demodulation. These types of modems are being used or considered for use in such applications as cellular radio and High rate Digital Subscriber Lines (HDSL).
In a Discrete Multitone system, the input bit stream is first serial-to-parallel converted. The parallel output is then grouped into N groups of bits corresponding to the number of bits per symbol. Portions of bits are allocated to each DMT carrier or subchannel. The power transmitted over each subchannel corresponds to the number of bits transmitted over each DMT subchannel.
Like a single carrier system, a multicarrier data transmission system tries to maximize a data transmission or bit rate for a particular Bit Error Rate (BER) and a particular Signal to Noise Ratio (SNR). In theory, the total bit rate (transmitted over all of the sub-channels) is maximized if the bit error rates for all the subchannels are equal. The concern is how best to allocate bits to each subchannel to attain the same BER over all of the subchannels.
FIG. 1 shows an example Discrete Multitone (DMT) communication system in which the present invention may be advantageously employed. Transmitter 10 includes a serial-to-parallel converter 14, a multicarrier modulator 16, and a pretransmit processor 18. Receiver 12 includes a post channel processor 20, a multicarrier demodulator 22, and a parallel-to-serial converter 24. The transmitter and receiver are linked in this example by a digital subscriber line (DSL) or other form of communication channel 26. Serial input data at a rate of b.sub.total /T bits per second are grouped by converter 14 into blocks of b.sub.total bits for each multicarrier symbol, with a symbol period of T. The b.sub.total bits in each multicarrier symbol are used to modulate N separate carriers in modulator 16 with b.sub.i bits modulating the i.sup.-th carrier.
A preferred example embodiment uses an Inverse Discrete Fourier Transform (IDFT) during modulation to generate N.sub.s time-domain samples of a transmit signal for each block of b.sub.total bits, where N.sub.s is preferably equal to 2N. The corresponding multicarrier demodulator performs a Discrete Fourier Transform (DFT), where b.sub.i bits are recovered from the i.sup.-th carrier. As depicted in FIG. 2, the carriers or subchannels in a DMT system are spaced 1/T Hz apart across N/T Hz of the frequency band. More detailed discussion of the principles of multicarrier transmission and reception in general is given by J. A. C. Bingham in "Multicarrier Modulation for Data Transmission: An Idea Whose Time Has Come", IEEE Communications Magazine, Volume 28, Number 5, pp. 5-14, May 1990.
The general structure of a Discrete Multitone Modulation DMT system is illustrated in FIG. 3, where {X.sub.0,X.sub.1, . . . , X.sub.N-1 } are the original, complex, input data symbols, {x.sub.k } is the modulated data sequence (before cyclic prefix), {h.sub.k } is the discrete-time channel response, {n.sub.k } is the additive noise sequence, {y.sub.k } is the received sequence (after the removal of cyclic prefix), and {x.sub.0, x.sub.1, . . . ,x.sub.N-1 } are the decoded, complex data symbols. The p.sub.i 's and p.sub.i *'s in FIG. 3 are known as the modulating and the demodulating vectors, and preferably they are chosen to be orthonormal.
Adding the cyclic prefix is a discrete-time technique used to eliminate interblock interference (IBI) in the DMT system. The independent modulating and demodulating vectors in FIG. 3 are the IDFT and the DFT vectors, given by the following pair of relationships: ##EQU1##
A DMT system with N complex subchannels in the frequency domain requires a DFT size of 2N, and the forced conjugate symmetry in the frequency domain results in the desired real-valued time domain samples. In the preferred embodiment, IDFT and DFT are implemented with the well known IFFT and FFT algorithms using the approach disclosed in commonly-assigned "Method and Apparatus for Efficient Computation of Discrete Fourier Transform and Inverse Discrete Fourier Transform," U.S. patent application Ser. No. 08/887,467, (attorney docket 1410-340), filed on Jul. 2, 1997.
FIG. 4 is a more detailed block diagram showing the principal operative components of a basic DMT transmitter 30 and a basic DMT receiver 32 connected through a channel 34. Serial input data are grouped into blocks, converted to a parallel form, and appropriately encoded by an encoder 36. Each one of the N active subchannels contains a number of b.sub.k bits allocated to that subchannel. The total number of bits in a DMT symbol is therefore: ##EQU2##
Each of the N bit groups is mapped by the symbol into a two-dimensional signal constellation. The relation between the number of bits in each block of bits b.sub.k and the necessary number of signal points in a constellation M is given by: EQU M.sub.k =2.sup.b.sbsp.k (4)
The signal points in a constellation are typically arranged in a rectangular pattern for even values of b.sub.k and a cross for odd values of b.sub.k. Provided that the same signal energy is used for all constellations, the distance between neighboring signal points is reduced with increasing constellation size resulting in increased BER with the same signal-to-noise ration (SNR).
The output from the encoder is N complex numbers, one for each group of bits, which are then fed to a device that calculates the Inverse Discrete Fourier Transform (IDFT). The output is a real sequence that can be considered the superposing of N modulated orthogonal carriers spaced .DELTA.f apart.
The parallel IFFT output is converted back to a serial data stream by a converter 40. The digital modulated data stream is cyclically prefixed, converted to analog form by a digital-to-analog converter (DAC) 42, low-pass filtered at 44, and passed through a D.C. isolating transformer 46 during pre-transmit processing to produce an analog signal transmitted over a transmission channel 34.
At the receiver end, the received analog signal is passed through a D.C. isolating transformer and low-pass filter 48, converted to digital form by an analog-to-digital converter (ADC) 50, time domain pre-equalized by a finite impulse response (FIR) filter 52 to limit the effective memory of the channel, and stripped of the cyclic prefix during post-receive processing in converter 54. The resulting digital signals are demodulated by 2N FFT operation 56 and converted to parallel frequency domain signals. Since the amplitude vs. frequency and the delay vs. frequency responses of the channel are not necessarily constant across the entire used frequency band, the received signal will differ from the transmitted signal, and the parallel inputs to the decoder 58 will differ from those parallel outputs from the encoder 36. One form of equalization used to compensate these differences is a frequency domain equalizer (FEQ) which individually adjusts for the attenuation and delay of each of the carriers immediately before the parallel frequency domain signals are passed to the decoder. The frequency domain equalized signals are appropriately decoded and converted back to a serial form by the decoder 58. Ideally, the detected output serial data from the decoder 58 is the same as the input serial data to the encoder 36.
In a conventional single-carrier digital transmission system, such as a Quadrature Amplitude Modulation (QAM) system implemented with an equalizer or a encoder, the transmission bandwidth is determined by the symbol rate and the carrier frequency of the system. Unfortunately, variable symbol rate, single-carrier systems are still impractical to implement from a complexity standpoint with today's technology, and even if they are implemented, the granularity of possible symbol rates are typically very coarse. This is a direct consequence of the fact that for a fixed data rate, the symbol rate can only change in discrete multiples of b.sub.symbol /(b.sub.symbol .+-.1), where b.sub.symbol is the number of bits transmitted by each data symbol, provided that only signal constellations with integer numbers of bits are used.
Multicarrier modulation, however, offers much more flexibility in granularity because it acts on block symbols that consist of a much larger number of bits per symbol over a large number of carriers. Since different numbers of bits can be transmitted through the different carriers (subchannels), the multicarrier transceiver can control the transmission bandwidth. As a result, more data bits are transmitted through the better carriers, i.e., having a greater Signal to Noise Ratio (SNR), and less data bits are transmitted through the worse carriers, i.e., having a lower SNR as shown in FIG. 5. In this manner, optimal performance can be achieved, in terms of either maximizing total data throughput for a fixed system performance margin or maximizing overall system performance margin for a fixed target data rate under a fixed, total input power constraint and target bit-error-rate.
Various bandwidth/bit allocation optimization techniques for multicarrier modulation have been proposed for different applications. The theoretical optimal energy allocation is the well known water-pouring energy distribution as described for example in J. G. Proakis, (1995), Digital Communications 3.sup.rd edition, McGraw-Hill, New York. Conceptually, the water pouring energy distribution model is obtained by first inverting the channel SNR curve shown in FIG. 5 in the frequency domain and then pouring the available energy into the resulting curve. The final "water level" at each particular frequency/carrier/subchannel is the optimal amount of energy to use at that particular frequency/carrier/subchannel. The number of bits transmitted by each carrier is determined by the maximum number of bits that can be supported by each carrier, given the water-pouring energy distribution and the desired bit-error-rate of each carrier. While the water-pouring technique yields the optimal bit and energy allocations, and therefore the optimal transmission bandwidth, it is typically complex and impractical to implement.
Another multicarrier bandwidth optimization technique designed for voice-band modem applications, where only constellations with an integer number of bits are used, was proposed by D. Hughes-Hartogs and described in "Ensemble Modem Structure for Imperfect Transmission Media", European Patent Number 0 224 556 B1 (published October 1991). The basic idea behind Hughes-Hartogs' algorithm is to incrementally add, one bit at a time, the amount of data to be transmitted in each multicarrier symbol until a desired data rate or power constraint is satisfied. Furthermore, this algorithm always chooses the subchannel that requires the least amount of incremental power to support an additional bit at the given desired bit-error-rate. Hughes Hartogs' algorithm, however, is typically too slow in convergence, making it especially unsuitable for applications where there are large numbers of carriers and bits to be supported by each multicarrier symbol as pointed out in P. S. Chow, J. M. Cioffi, J. A. C. Bingham, "A Practical Discrete Multitone Transceiver Loading Algorithm for Data Transmission Over Spectrally Shaped Channels," IEEE Transactions on Communications, Vol. 43, No. 2/3/4, pp. 773 775, 1995. Also, the channel response is assumed to be fixed, i.e., time-invariant after training, which is not a good assumption for many applications, e.g., mobile radio communications.
In order to achieve faster convergence at the expense of a slight performance degradation, Chow et al. proposed a three-step bit loading algorithm. First, an optimal system performance margin is found; second, convergence is guaranteed with a suboptimal loop; and third, the energy distribution is adjusted for each subchannel if the transmission system is constrained by the total transmit power.
However, Chow's bitloading algorithm requires computationally complex steps best run on a microprocessor and a number of iterative elements that may be excluded. Both requirements increase the system cost and reduce speed. The bit loading procedure in accordance with the present invention minimizes computational complexity and permits execution by specific hardware which is faster than programmed microprocessor driver solutions. Also those parts of the algorithm that are best run on a microprocessor are of such basic character that only a rudimentary, inexpensive device is necessary.
It is an object of this invention therefore to provide optimal bitloading using less computational power and at a fast rate.